The present invention relates to improved FET structures and methods of making same. More particularly, the present invention pertains to a self-aligned silicon gate FET structure and a method of making same.
The physics, performance, and use of FET structures or elements are well known in the semiconductor arts and therefore will not be described herein. A significant amount of low cost, large scale integrated electronics is based upon the metal oxide semiconductor (MOS) field effect transistors (FET). An article describing such devices is, "Silicon-Gate Technology", by Vadasz et al., IEEE Spectrum, Oct. 1969, pp. 28-35. In particular, the article points out the advantages of self-aligned FET's utilizing silicon nitride (Si.sub.3 N.sub.4) and silicon dioxide (SiO.sub.2) as the gate insulator and heavily doped polysilicon as the gate conductor.
The term self-alignment generally means that the gate structure, including the gate insulator and conductor, is formed prior to the drain and source diffusions. This technique permits the gate structure to act as part of the diffusion mask thereby permitting self-alignment of the diffused regions.
The gate insulator is formed over the channel region by placing a silicon wafer into an oxidizing ambient and growing a thin layer of silicon dioxide of about 0.1 micrometers thick. Subsequently, a thin layer of silicon nitride, another insulator, is deposited onto the thin silicon dioxide layer. The gate conductor is formed by next depositing a layer of heavily doped polysilicon on top of the silicon nitride. Masks are subsequently used to etch away the portions of the polysilicon, silicon nitride, and silicon dioxide, which are unwanted. The latter technology is believed to provide some of the advantages over the technology which preceded it. One advantage is reduction in parasitics. Another is a lowering of the threshold voltage. The latter is believed due to the use of silicon nitride with the silicon oxide. The silicon nitride also provides an advantage in connection with the etching of the polysilicon conductor. Most of the chemicals which etch polysilicon will also attack silicon dioxide but will not attack silicon nitride. Consequently, in the absence of the silicon nitride between the thin silicon dioxide layer and the polysilicon layer, removal of the polysilicon in certain regions would also result in removal of the silicon dioxide. In integrated circuits this may not be desirable.
While the structure mentioned above has certain definite advantages, it is not free from all problems. One problem is that the gate insulator formed by the combination of silicon dioxide and silicon nitride causes the threshold voltage of the FET device to drift and therefore become somewhat unstable. The problem of drift is not as prevalent when the silicon nitride is not used. It is known in the prior art to use as the gate insulator a layer of phospho-silicate glass without any silicon nitride to improve the stability and reliability of the gate insulation.